The present invention relates to a MOS technology integrated circuit reenergizing circuit (metal, oxide, semiconductor), more particularly to a CMOS (Complementary MOS) technology circuit.
In certain types of integrated circuits, and particularly those containing flip-flops, it is important that certain points of the circuit have a clearly defined logical state when the circuit is energized following a power cut-off. Indeed, it is important to prevent uncertain or incorrect logic states from appearing during the build-up of the power supply voltage and having subsequent effects on the operation of the circuit.
However, the state of the nodes in a logic circuit can only assume a definite value if the power supply voltage of the circuit exceeds a minimum value. As an example, for a logic circuit manufactured according to the C-MOS technology, this minimum value is 3 Volts. For a lower voltage, the node potentials are variable, depending more upon the circuit capacitive coupling than they do upon purely logical data. In addition, these potentials may differ from one circuit to another according to line production.
To overcome this drawback, a reenergizing circuit is thus used supplying a positioning pulse when the power supply voltage reaches a high enough value to permit the positioning of the logic circuit using a no-load operating cycle. To operate correctly, the reenergizing circuits must meet a certain number of criteria. They must be fast in order to operate with power supply rise times included between one microsecond and one second. They must trigger for a voltage greater than 3 Volts but less than 4.5 Volts. In addition, the triggering pulse must reach the circuit before the power supply has become stabilized at its final value. Further, they must be able to operate in a temperature range included between -55 C. and +125 C.
It is the object of the present invention to provide a new reenergizing circuit which meets the above-defined criteria.